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Espressif Systems /ESP32-S3 /I2S0 /TX_CONF1

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Interpret as TX_CONF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TX_TDM_WS_WIDTH 0TX_BCK_DIV_NUM 0TX_BITS_MOD 0TX_HALF_SAMPLE_BITS 0TX_TDM_CHAN_BITS 0 (TX_MSB_SHIFT)TX_MSB_SHIFT 0 (TX_BCK_NO_DLY)TX_BCK_NO_DLY

Description

I2S TX configure register 1

Fields

TX_TDM_WS_WIDTH

The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
TX_BCK_DIV_NUM

Bit clock configuration bits in transmitter mode.
TX_BITS_MOD

Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
TX_HALF_SAMPLE_BITS

I2S Tx half sample bits -1.
TX_TDM_CHAN_BITS

The Tx bit number for each channel minus 1in TDM mode.
TX_MSB_SHIFT

Set this bit to enable transmitter in Phillips standard mode
TX_BCK_NO_DLY

1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data